1. Field of the Invention
The present invention relates to an image sensor and fabricating method thereof, and more particularly, to a CMOS image sensor and fabricating method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for the CMOS image sensor including a microlens formed of or comprising silicon oxide.
2. Discussion of the Related Art
Generally, an image sensor is a semiconductor device for converting an optical image to electric signals. Image sensors may be categorized mainly into charge coupled devices (CCDs) and CMOS (complementary metal oxide silicon) image sensors.
In the charge coupled device (CCD), a plurality of photodiodes (PD) for converting an optical signal to an electric signal are aligned in a matrix form. The CCD consists of a plurality of vertical charge coupled devices (VCCD), a horizontal charge coupled device (HCCD) and a sense amplifier. Each of a plurality of the VCCDs is provided between vertical photodiodes arranged in a matrix form and plays a role in transporting a charge generated from the corresponding photodiode in a vertical direction. The HCCD plays a role in transporting a charge transported by each of the VCCDs in horizontal direction. And, the sense amplifier outputs an electric signal by sensing the charge transported in horizontal direction.
Yet, the above-described CCD has a relatively complicated driving mechanism, consumes relatively high power, and needs a multi-step photo process. Hence, it is disadvantageous in that the CCD fabricating process may be relatively complicated. Moreover, it is difficult to integrate a control circuit, a signal processing circuit, an analog/digital (A/D) converter and the like on a CCD chip. Hence, it may be challenging to reduce the size of the CCD product.
Recently, attention has been paid to CMOS image sensors as a next generation image sensor to overcome the disadvantages of the CCD. The CMOS image sensor is a device adopting a switching system for sequentially detecting and/or processing an output of each unit pixel by MOS transistors. The MOS transistors are generally formed according to the number of unit pixels on a semiconductor substrate, using CMOS technology that can also be used to form control circuits, signal processing circuits and the like as peripheral circuits.
Namely, the CMOS image sensor implements an image by capturing light-induced charges in a photodiode, sensing the charges using one or more MOS transistors in the unit pixel, and then detecting an electric signal from each unit pixel using a switching system.
As the CMOS image sensor is made using CMOS fabrication technology, it has advantages such as relatively small power consumption, a relatively simple fabrication process using a relatively small number of photolithography process steps, and the like. Moreover, the CMOS image sensor, for which a control circuit, a signal processing circuit, an A/D converter and the like can be integrated on a CMOS image sensor chip, has an advantage in facilitating a reduction in the size of the image sensor product. Therefore, the CMOS image sensor is applicable to various fields including digital still cameras, a digital video cameras, and the like.
FIG. 1 is an exemplary circuit diagram of a four-transistor (4T) type unit pixel for a CMOS image sensor, and FIG. 2 is an exemplary layout of a general 4T type CMOS image sensor unit pixel.
Referring to FIG. 1, a unit pixel 100 of a CMOS image sensor consists of a photodiode 10 as a photoelectric converting unit and four transistors. In this case, the four transistors include a transfer transistor 20, a reset transistor 30, a drive transistor 40 and a select transistor 50. An optional load transistor 60 is electrically connected to an output terminal OUT of the unit pixel 100. In this case, the reference ‘FD’ indicates a floating diffusion region, ‘Tx’ indicates a gate voltage of the transfer transistor 20, ‘Rx’ indicates a gate voltage of the reset transistor 30, ‘Dx’ indicates a gate voltage of the drive transistor 40, and ‘Sx’ indicates a gate voltage of the select transistor 50.
A unit pixel of a general 4T type CMOS image sensor, as shown in FIG. 2, includes an active area defined by a device isolation area (not shown, but formed in parts or regions of the unit pixel other than the active area). A single photodiode PD is formed in a relatively wide part of the active area, and gate electrodes 23, 33, 43 and 53 of four transistors are formed on/over the remaining part of the active area. Namely, the transfer transistor 20 includes the gate electrode 23, the reset transistor 30 includes the gate electrode 33, the drive transistor includes the gate electrode 43, and the select transistor 50 includes the gate electrode 53. In this case, source/drain (S/D) regions are formed in the active area adjacent to each of the transistor gates, but not beneath each of the gates 23, 33, 43 and 53, by ion implantation.
A general image sensor including a plurality of pixels intensively arranged in rows and columns includes a photodiode PD generating photoelectrons by detecting external light, a floating diffusion region FD delivering an electric charge generated from the photodiode, and a transfer transistor Tx provided between the photodiode PD and the floating diffusion region FD to transfer the electric charge generated from the diode PD to the floating diffusion region FD.
An operational sequence of the above-configured CMOS image sensor is explained in brief as follows. First of all, as the reset transistor Rx is turned on, a potential of an output floating diffusion node becomes VDD. In this case, a reference value is detected.
Subsequently, if light enters the photodiode PD, which is a light receiving unit, from outside of the image sensor, electron-hole pairs (EHPs) are generated in proportion to the light. By the signal charge generated from the photodiode PD, a potential of a source node of the transfer transistor Tx varies in proportion to a quantity of the generated signal charge.
If the transfer transistor Tx is turned on, the accumulated signal charge is transferred to the floating diffusion region FD. A potential of the output floating diffusion node is changed in proportion to the transferred signal charge quantity as soon as a gate bias of the drive transistor Dx is changed. This eventually results in a change of a source potential of the drive transistor Dx. In this case, if the select transistor Sx is turned on, data is read out to a column read circuit of the image sensor.
Subsequently, as the reset transistor Rx is turned on, the potential of the output floating diffusion node becomes VDD. And, the above process is repeated.
A CMOS image sensor according to the related art is explained with reference to FIG. 3 as follows.
Referring to FIG. 3, a CMOS image sensor according to the related art consists of a device isolation layer 102 in a device isolation area of a semiconductor substrate 101, a plurality of photodiode regions 103 in the active areas of the semiconductor substrate 101, an insulating interlayer 104 over the semiconductor substrate 101 including the photodiode regions 103, a first planarization layer 105 on the insulating interlayer 104, a color filter layer 106 (containing red [R], green [G] and blue [B] color filters) on the first planarization layer 105 to correspond to the photodiode regions 103, respectively, a second planarization layer 107 over the semiconductor substrate 101 including the color filter layer 106, and a plurality of microlenses 108 on the second planarization layer 107 to correspond to the color filters in the color filter layer 106. In this case, various transistors (not shown in the drawing) and metal wires (not shown in the drawing) are formed on, in or over the active areas (and, in the case of the metal wires, over the device isolation areas) of the semiconductor substrate 101.
In the above-configured CMOS image sensor according to the related art, one color filter in the color filter layer 106 is formed per color over the photodiode region 103 to receive a red, green or blue (R/G/B) signal. To receive more light, the microlens 108 is provided over the light-receiving unit. The respective signals are connected to an image processing circuit provided outside the light receiving unit via a plurality of metal wires and are then combined into a single image.
If the microlens shown in FIG. 3 is formed of silicon oxide instead of the conventional organic substance, it is able to prevent the microlens from being contaminated by particles generated from sawing the wafer in the course of packaging a device. However, the oxide substance for the microlens may be deposited at a relatively low temperature, resulting in a layer quality that is not as dense as possible. As a consequence, pin holes exist within the microlens layer. Due to this problem, chemicals may penetrate through the oxide microlens during a wet process to dissolve organic substances of the second planarization layer (or an overlying resist or resist pattern), whereby the microlens 108 may peel off from the second planarization layer 107.
Moreover, when certain oxides are deposited at a low temperature (e.g., to form the microlens in the related art process), it can be observed that many pin holes exist in the silicon oxide. If a wet process is further performed, the planarization layer 107 may be partially dissolved, whereby the microlens 108 may exfoliate or peel off from the planarization layer 107.